The present invention relates in general to semiconductor technology and in particular to a structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices.
An important parameter in trench power metal-oxide-semiconductor field-effect transistors (MOSFETs) is the total gate charge. In some applications of conventional trench power MOSFETs, such as DC-DC converters, the lower the gate charge the better the efficiency of the overall design. One technique in reducing the gate charge is to reduce the gate to drain capacitance by using a thick dielectric along the bottom of the gate trench.
A conventional local oxidation of silicon (LOCOS) process is commonly used to form the thick dielectric along the bottom of the trench. This process often involves forming a silicon nitride layer along the trench sidewalls to protect the sidewalls during formation of the thick dielectric. However, the anisotropic etch used to remove the silicon nitride along the bottom of the trench also removes the silicon nitride extending over the mesa surfaces adjacent the trenches. As a result, during formation of the thick dielectric along the bottom of the trench, a similarly thick dielectric is formed over the mesa surfaces adjacent to the trench.
A thick dielectric over the mesa surfaces can cause a number of problems. First, the thick dielectric typically overhangs the upper trench corners, which can cause voiding in the gate polysilicon. Additionally, removing the thick dielectric from over the mesa surfaces requires substantial etching, which can also etch the gate oxide along the upper trench sidewalls leading to gate shorts and yield problems. Also, variability in the thickness of the dielectric over the mesa surfaces can cause variability in the body implant process causing variability in the electrical parameters of the device.
Thus, there is a need for improved techniques for forming a thick dielectric along the bottom of a gate trench.